This invention relates to an analog-to-digital converter for converting an analog input signal into a digital output signal in a series of successive conversion steps, comprising
comparison means for comparing in a plurality of conversion steps the analog input signal with at least two reference signals defining at least three sub-ranges of a fraction of an input-signal range, PA1 output means for generating the digital output signal on the basis of comparison signals generated by the comparison means in the successive conversion steps. PA1 generator means for generating, on the basis of the comparison signal generated in a conversion step, new reference signals for the next conversion step, the new reference signals defining a new fraction of the input signal range for the next conversion step, which new fraction overlaps one of the sub-ranges of the relevant conversion step. PA1 first storage means for the storage of a fraction signal corresponding to the magnitude of the fraction, PA1 second storage means for the storage of a level signal which is related to the fraction, PA1 conversion means for converting the fraction signal and the level signal into the reference signals, and PA1 adaptation means for adapting the fraction signal and the level signal to the next conversion step on the basis of the comparison signal of the relevant conversion step. PA1 first supply means for supplying to the first storage means, upon completion of a conversion step, a fraction signal multiplied by an adaptation factor, PA1 second supply means for supplying to the second storage means, upon completion of the conversion step, the sum of the level signal and the product of the fraction signal and the comparison signal multiplied by a weighting factor. PA1 a first and a second digital-to-analog converter for converting the fraction signal and the level signal into an analog window signal and an analog shift signal respectively, and in that the comparison means comprise PA1 a parallel analog-to-digital converter for converting a range of the analog input signal, which range is defined by the window signal and the shift signal, into the comparison signal. PA1 multiplication means for multiplying the fraction signal by a coefficient to generate a product signal in a predetermined number of successive intermediate steps during the conversion step, PA1 adding means for forming the sum of the level signal and the product signal so as to obtain a sum signal, and PA1 a digital-to-analog converter for converting the sum signal into the reference signal, and in that the comparison means comprise PA1 a comparator for comparing the analog input signal with the reference signal, PA1 third storage means for the storage of the successive values of a decision signal generated by the comparator in the intermediate steps and decoder means for decoding the values of the decision signal into the comparison signal.
Such an analog-to-digital converter is of the successive-approximation type (SA), in which the analog input signal is converted into the digital output signal in a series of successive conversion steps. In each conversion step the value of one bit of the output signal is determined, starting with the most significant bit (MSB), in that each time one bit of a successive approximation register (SAR), whose bits have been reset to zero when conversion begins, is set to one, the digital value in the register being converted into an analog reference signal via a digital-to-analog converter (DAC), and the analog input then is compared with said reference signal with the aid of comparison means in the form of a comparator. The comparator generates a comparison signal on the basis of which a decision is taken either to maintain the relevant bit in the SAR as a one or to reset it to zero. Upon termination of the conversion steps the content of the SAR corresponds to the digital output signal. In each subsequent conversion step in these successive-approximation converters, a fraction of the input signal range is selected which is equal to half the fraction of the preceding conversion step. The reference voltage divides the fraction into two equal sub-ranges. By means of the comparison signal the comparator then indicates in which sub-range the input signal is situated. This sub-range becomes the new fraction for the next conversion step.
It is also possible to determine a plurality of bits at a time in every conversion step. EP 0,153,778 which corresponds to U.S. Pat. No. 4,649,371 (3/10/87) discloses a successive-approximation analog-to-digital converter which determines 2 bits at a time in every conversion step. The comparison means then comprise a 2-bit parallel analog-to-digital converter having three comparators and in every conversion step a fraction of the input signal range is divided into four equal sub-ranges. The comparators in the parallel converter decide in which sub-range the input signal is situated and indicate this by means of a 2-bit comparison signal on the basis of which the values of the 2 bits of the SAR, and hence those of the output signal, are defined. Moreover, the sub-range thus found is selected as the new fraction for the next conversion step.
A drawback of the prior-art successive-approximation converters is that an erroneous decision irrevocably results in an erroneous bit being stored in the SAR, so that a wrong output signal is supplied. A first cause of incorrect decisions may be that the comparator is too slow. Within every conversion step a specific window is available within which the comparator is given the opportunity to form an output signal on the basis of which a decision is taken. In every conversion step the output signal of the comparator will change to one of two extreme values and thus pass a decision threshold, depending on the difference between the input signal and the reference signal. A difference equal to half a quantisation step should already cause the output signal to pass the decision threshold so far that an accuracy corresponding to half the least significant bit (LSB) is obtained. The output signal of a slow comparator cannot track the changes in the differences rapidly enough, so that the decision threshold is not passed in due time and erroneous decisions are taken. In particular, if the analog input signal has a value corresponding to approximately the MSB, the comparator should be capable of responding rapidly and accurately, immediately after the largest possible variation of the reference signal.
Another cause of erroneous decisions may be due to the presence of noise on the analog input signal, on the reference signal and in the comparator. Since the comparator should have a wide frequency pass band to enable it to respond rapidly, the noise in this frequency band will also affect the decision accuracy. Although, in particular, the comparator(s) used constitute an important error source, other components of the successive approximation converter may also give rise to an incorrect decision. For example, the DAC which generates the reference voltages also has a certain response time to changes at its digital input. Even components whose operation is purely digital, such as the SAR, may constitute an error source if the conversion speed is higher than a certain value.